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calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
VHDL1
- a simple calculator with vhdl operators performing calculator operation
sdfsugfus
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
libraryManageSystem
- 实现一个图书馆管理系统，功能比较完善，实用性比较强。-The realization of a library management system, features a relatively complete, practical, strong.
Crc_Parallel
- CCITT Parallel CRC 16-bit
test
- 简易计算器 2位数字的加减乘除 用VHDL编程 在实验箱上实现-Simple Calculator 2-digit addition and subtraction, multiplication and division using VHDL programming to achieve in the experimental box
CaculatorBasedonVHDL
- 用VHDL编写的计算器，供下载到学习板上使用，芯片型号请在工程中查看。可以实现加减与或比较-Written by VHDL calculator, available for download to learn to use the board, the chip model in the project view. Comparison of addition and subtraction can be achieved with or
zzchufaqi
- vhdl 除法器 eda课程设计用。 设计一个两个五位数相除的整数除法器。用发光二极管显示输入数值，用7段显示器显示结果十进制结果。除数和被除数分两次输入，在输入除数和被除数时，要求显示十进制输入数据。采用分时显示方式进行，可参见计算器的显示功能。-divider vhdl eda curriculum design purposes. Design a two five-digit integer divider division. Enter the value with the lig
cal
- 运用quartusII vhdl语言做成的计算器-Made use of quartusII vhdl calculator language
Cal2
- 课堂学习自制VHDL计算器小程序，使用4*4键盘，A加法,B乘法,C退格,E等于,F清零。-A program of Calculator made in VHDL course in school, using 4*4 keyboard.
123
- 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
jianyijisuanqi
- 用VHDL实现简易计算器，实现加法、减法、乘法、除法的功能。-Use VHDL to realize simple calculator, can realize the function of addition, subtraction, multiplication, and division.
calc_16_01_14
- A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
FPGADE270CACULATOR
- 本文介绍了一个简单的计算器的设计，该设计采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在LCD1602上。-This article describes a simple calculator design that uses a field programmable logic device FPGA design and VHDL language based on arithmetic functions, and decimal display
7-timer
- 本代码是实现计算器的功能，用的是VHDL语言编写，全部实现过程都在这里面。-This code is to achieve the functions of the calculator, using the VHDL language, to achieve full process on the inside
xuliejiancejisuanqikongzhiqi
- VHDL序列检测器，计算器，控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
calculate
- 基于VHDL，通过拨码开关实现数字输入，通过6位数码管实现输出。实现计算器的简单加、减、乘、除的基本功能-Based on VHDL, by DIP switch digital inputs, 6 digital control to achieve through output. Achieve a simple calculator to add, subtract, multiply, in addition to the basic functions
entity-fp-is
- 简易计算器4*4矩阵键盘输入,多个数值vhdl代码-Simple calculator 4* 4 matrix keyboard input, multiple values vhdl codes
AnJian_1602
- 计算器设计。采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形，并下载到试验箱,用实验箱上的按键开关模拟输入，用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能，其结果简单，易于实现。-Calculator design. Using a field programmable logic d
jisuanqi
- VHDL语言编写的计算其程序，可实现简单的加减乘除运算。-Functions to achieve universal calculator